advantages of vhdl over verilog

[Deepika.R]

can anyone state advantages of vhdl programming over verilog? i know verilog is has many advantages than vhdl... but i have done project based using vhdl coding.. so want to know its advantages..

 

[sabin14]

This Comparison might help you:
https://www.angelfire.com/in/rajesh52/verilogvhdl.html

 

[std_match]

I use VHDL, and I understand Verilog have some "problems":

You don't have to declare signals. If you make a typo, a new net is created and it is not an error.

If you connect buses of different widths to each other, it is not flagged as an error.

A reset signal must be declared as an edge, but I think it works as a level anyway (which you want).

Blocking and non-blocking assignments are very confusing and hard to read.
VHDL has a more elegant solution with variables (=blocking) and signals (=non-blocking).

Verilog code can have a "race" condition, where the simulation result depends on the execution order. That is impossible in VHDL.

As you can see, I am biased towards VHDL :razz:

 

[TrickyDicky]

VHDL has good points, Verilog has good points. They both also have bad points. But at the end of the day they both can be used to describe the same circuits.

So go with one you are comfortable with and one that everyone else you know/work with uses.

 

[imbichie]

If we talking in terms of Finding error and Debugging, VHDL is far better than Verilog. In verilog minute errors wont popup during the compilation time. It will popup at the time of synthesis only.
This is why in Almost all the defense, Avionics and Aircraft systems are using only VHDL as the HDL.

But verilog is easy to learn and there is no need of including the standard library packages in each file.