jimjim2k
Advanced Member level 3

advanced seminar topics in vlsi
Hi
PARWAN is a simple accumulator-based processor
1. h**p://aspire.ucsd.edu/~lichen/260c/parwan/
A. VHDL code
(Synthesizable RTL description)
2. h**p://aspire.ucsd.edu/~lichen/260c/parwan/rtl
(Gate level description)
3. h**p://aspire.ucsd.edu/~lichen/260c/parwan/gate/cpu.vhd
(atpg library used for fault simulation)
4. h**p://aspire.ucsd.edu/~lichen/260c/parwan/atpg.lib
* -> t
tnx
Hi
PARWAN is a simple accumulator-based processor
1. h**p://aspire.ucsd.edu/~lichen/260c/parwan/
A. VHDL code
(Synthesizable RTL description)
2. h**p://aspire.ucsd.edu/~lichen/260c/parwan/rtl
(Gate level description)
3. h**p://aspire.ucsd.edu/~lichen/260c/parwan/gate/cpu.vhd
(atpg library used for fault simulation)
4. h**p://aspire.ucsd.edu/~lichen/260c/parwan/atpg.lib
* -> t
tnx