You want to present a bunch of load pull data on the gate side of the transistor and design a matching network. Since it's push-pull network the design is symmetrical. You can simplify it but just simulating the upper half or the lower half. In that case, it's just a 1 port file. The better way to do it is by calling a DAC component and load it up the CITI or touchstone file and pass it through the TERM component. This way you have more control over the variable "Zin" for sweeps.