I got what you mean now. actually, the layout follows good RF layout guidelines which avoid long interconnects and parallel ground plane underneath component pads and so on. However, parasitic inductor and capacitance are unavoidable at high frequency (2.5GHz) regardless of how good your layout is. my question is what can we do post layout to optimize the layout with parasitics. This is because component values given by "smith chart utility" is not giving good results. a method to optimize the layout to meet the performance.