ADPLL Output lock condition

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pmuppala

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Hi,

I am doing an adpll in 90nm technology. I am not able to understand how to lock the DCO divider output to REF frequency. DCO divider output is oscillating up and down around the target frequency but not locking to it. Please do post if you think i have missed something.

Thanks,
Muppala.
 

It also needs stability analysis. Pls derive behavior model and have simulation to check phase margin.
 

Thanks for your response.

In the attached image u can see how the transient response looks like. The blue line indicates the reference frequency and the red line is the FB freq which is oscillating around Target.

Sorry, I could not understand you properly. I figured that you want me to write a behavioral code of the circuit and do simulation on it to find phase noise. Please correct if i got it wrong.
 

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