these ports can be connected to cpu.
rx_data_out : out std_logic_vector(7 downto 0); -- Received Data
rx_data_en : out std_logic; -- Received data enable control signal
rx_ovf_err : out std_logic; -- Received data over frame error detected
rx_parity_err : out std_logic; -- Received data parity error
tx_data_in : in std_logic_vector(7 downto 0); -- Transmited data
tx_data_en : in std_logic; -- Transmited data latch enable
tx_ch_rdy : out std_logic; -- Transmition channel ready status signal
-- Control signals ....these you can give directly...e.g. you want odd parity set parity_type as one in vhdl..
baud_sel : in std_logic_vector(3 downto 0); -- Baud rate value see Note
parity_en : in std_logic; -- Enable parity control signal active HIGH
parity_type : in std_logic); -- 1:ODD parity / 0:EVEN parity
end entity;
These two signal are RS232 I/O interface.
rx_data_serial : in std_logic; -- Received Serial data from RS232(RxD line)
tx_data_serial : out std_logic; -- Transmited Serial data to RS232(TxD line)