Additive latency for DRAM READ and WRITE commands

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AL=1 seems to be handled specially. However, the same information can't be found in newer Micron DDR2 datasheets, thus I wonder if it applies to all devices.
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TN-47-10 isn't available at micron.com, but several other TN-47-xx notes are. Suggests that it has been withdrawn.
 
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