Well, of course it is. This is synchronous logic, so you apply inputs "a" and "b", and the sum of those will appear on "c" the very next clock cycle.
Put another way, you have your a and b inputs ... then follows the actual combinational logic that does the addition. You don't see that in simulation, but should you synthesize it to real hardware this combinational logic will be there. And the outputs of that combinational logic is going to the input of a bunch of flip-flops aka registers aka that output logic. And then on the next posedge of your clock this result is clocked into the registers, and that is the result you see here in your sim with the 1 cycle delay.