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-- Ports declarations
parity_en_i : in std_logic;
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stop_bit_count_i : in std_logic;
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architecture arc of module_arch is
-- Signal declarations
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signal tx_data_length : unsigned(3 downto 0);
signal data_length : unsigned(3 downto 0);
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signal parity_en : integer range 0 to 1;
signal stop_bit_count : integer range 0 to 1;
begin
parity_en <= 1 when parity_en_i = '1' else 0;
stop_bit_count <= 1 when stop_bit_count_i = '1' else 0;
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tx_data_length <= 1 + data_length + to_unsigned(parity_en, 1) + 1 + to_unsigned(stop_bit_count, 1);
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