Add EMIF IP to VHDL code

[nelky22]

Hi experts and all Sifus,
I have an issue here.

I've used Quartus Prime Pro to create and generate EMIF ip. EMIF stands for external memory interface. I even have compiled successfully and assigned the pins following pins in the Agilex 7 development board schematics.

Currently, I am supposed to use the EMIF IP generated to perform a write operation to DDR4. I can see some VHDL code generated. I don't know if that is something useful.

I just don't know how to include the EMIF IP into my VHDL code and do the writing operation.

I don't know if my thinking is correct this way.

Could you please help me?

 

[dpaul]

I just don't know how to include the EMIF IP into my VHDL code and do the writing operation.

Instantiate the IP in your own VHDL and drive the ports of the IP
How to instantiate - https://vhdlwhiz.com/entity-instantiation-and-component-instantiation/

 

[nelky22]

Instantiate the IP in your own VHDL and drive the ports of the IP
How to instantiate - https: // vhdlwhiz.com/entity-instantiation-and-component-instantiation/

Hi Dpaul,
Thanks for coming back to me.

I just don't know how to do it. It generated 3 files,
ed_synth_emif_fm_0.vhd
ed_synth_emif_cal.vhd
ed_synth_inst.vhd

I just don't know how to use these files or one of these files to perform write / read operation to the DDR4. Do you have any sample code?

Regards,

 

[barry]

without seeing your code it’s impossible to tell, but i might GUESS that the ed_synth_inst moduleMIGHT be what you need to instantiate in your code since it has “inst” in the name.

But i suspect the documentation for the ip might give you a clue

 

[nelky22]

without seeing your code it’s impossible to tell, but i might GUESS that the ed_synth_inst moduleMIGHT be what you need to instantiate in your code since it has “inst” in the name.

But i suspect the documentation for the ip might give you a clue

Hi barry,
Thanks for coming back.

I attach the generated code here for your reference. I don't know which one to use to perform a write / read operation.

Could you please guide me?

Regards,

 

[FvM]

ed_synth_inst.vhd is the top entity of the example design. As you see, it includes the memory module pins, some test status outputs and (in your specific implementation) a traffic generator control interface, but no data bus.

You need to look deeper into the structure of the example design to understand why is it so. It consists of the emif controller itself, a calibration controller and the traffic generator to test the RAM. If want you use the memory for a real data storage application, you'll instantiate emif and calibration controller but no traffic generator.

I don't know what your application is. You probably noticed that the emif controller has a 576 bit wide data interface (8x72) due to translating hide speed DDR4 interface to manageable core clock speed, in this case 300 MHz.