ed_synth_inst.vhd is the top entity of the example design. As you see, it includes the memory module pins, some test status outputs and (in your specific implementation) a traffic generator control interface, but no data bus.
You need to look deeper into the structure of the example design to understand why is it so. It consists of the emif controller itself, a calibration controller and the traffic generator to test the RAM. If want you use the memory for a real data storage application, you'll instantiate emif and calibration controller but no traffic generator.
I don't know what your application is. You probably noticed that the emif controller has a 576 bit wide data interface (8x72) due to translating hide speed DDR4 interface to manageable core clock speed, in this case 300 MHz.