ADC with Qsys tool Altera

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grezzoman

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Hello friends!

Since I need to add an ADC in a FPGA project (MAX 10, quartus 17) I tried to donwload some example from altera cloud, like the one below:

https://cloud.altera.com/devstore/p...for-use-with-board-test-system-monitor-panel/

After compilation quartus reports that no logic depends on input clock (to ADC) and that all pin connected to tha ADC dataout are stacked@gnd.

No ADC example from altera cloud help me, always the same problem...

Can somebody help me in this trip? I'm new in FPGA programming and I can't understand why I'm wrong..

Thanks in advance,

Regards!
 

grezzoman said:
I'm new in FPGA programming and I can't understand why I'm wrong..
Click to expand...

And I can't understand what your question is, nor do you supply any useful information to help answer your question (whatever the question is supposed to be).
 

you can use a microcontroller to read the analog input then feed it to the FPGA/CPLD

if you don't want that solution, you can buy a ADC IC and interface with it.
 

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