adc controller vhdl help urgent

[mtech84]

hello all this is the code below i am getting error
Error (10405): VHDL error at CONTROLLER.vhd(68): can't determine type of object at or near identifier "to_bitvector" -- found 0 possible type

help me to remove the error to_bitvector what shall i use i tried just bit does not work..
code:===============================
LIBRARY IEEE; USE IEEE.std_logic_1164.ALL;
USE STD.textio.ALL;


--------------------------------------------------------------------------------
-- ENTITY DECLARATION
--------------------------------------------------------------------------------

ENTITY CONTROLLER IS
GENERIC (
CONSTANT sWait : integer := 0;

CONSTANT sSample : integer := 1;

CONSTANT sConv : integer := 2;

CONSTANT sDone : integer := 3);

PORT ( CLK : IN bit; --clock input
go: IN bit; -- go =1 to perform conversion
valid : OUT bit; -- valid = 1 when conversion finished
result: OUT bit_vector(7 downto 0); --8 bit result
sample: OUT bit; -- to s & H circuit
valu: OUT bit_vector(0 downto 0); -- to dac
cmp:IN bit); -- from comparator



--LEDG : OUT STD_LOGIC_VECTOR(8 DOWNTO 5);
--HEX0 : OUT STD_LOGIC_VECTOR(0 TO 6)

END CONTROLLER;

ARCHITECTURE CONTROLLER OF CONTROLLER IS

SIGNAL state : bit_vector(1 DOWNTO 0); --currently state in state machine
SIGNAL mask : bit_vector(7 DOWNTO 0); --bit to text in binary search
-- Intermediate signal for valid
SIGNAL valid_xhdl1 : bit;
-- Intermediate signal for result
SIGNAL result_xhdl2 : bit_vector(7 DOWNTO 0);
-- Intermediate signal for sample
SIGNAL sample_xhdl3 : bit;
-- Intermediate signal for value
SIGNAL value_xhdl4 : bit_vector(7 DOWNTO 0);
---state assignment

--CONSTANT sWait : integer := 0;
--CONSTANT sSample : integer := 0;
--CONSTANT sConv : integer := 0;
--CONSTANT sDone : integer := 0;

BEGIN

valid <= valid_xhdl1;
result <= result_xhdl2;
sample <= sample_xhdl3;
valu <= value_xhdl4;

-- synchronous design

PROCESS

BEGIN

WAIT UNTIL (CLK'EVENT AND CLK = '1');
IF (NOT go ='1') THEN
state <= to_bitvector(sWait,2); --stop and reset if go=0
ELSE
CASE state IS
--choose next state in state machine

WHEN to_bitvector(sWait,2) =>
state <= to_bitvector(sSample,2);
WHEN to_bitvector(sWait,2) =>
--start new conversion so
state <= to_bitvector(sConv,2); --enter convert state next
mask <= "10000000"; --reset mask to msb only
result_xhdl2 <= "00000000"; -- clear result
WHEN to_bitvector(sConv,2) =>

--set bit if comparator indicates input larger than value currently under consideration, else leave a bit clear

IF (cmp = '1') THEN
result_xhdl2 <= result_xhdl2 OR mask;
END IF;

--shift mask to try next bit next time

mask <= ShiftRight(mask , 1);
--finished once LSB has been done

IF (mask(0) = '1') THEN
state <= to_bitvector(sDone,2);
END IF;

WHEN to_bitvector(sDONE,2) =>

WHEN OTHERS =>
NULL;

END CASE;

END IF;
END PROCESS;

sample_xhdl3 <= to_bit(state = to_bitvector(sSample,2));

value_xhdl4 <= result_xhdl2 OR mask;

valid_xhdl1 <= to_bit(state = to_bitvector(sDone,2));


END CONTROLLER;

==================

Added after 52 minutes:

plz reply...... thx.....

 

[FvM]

You are only using std_logic_1164 library, it has no numeric data types and thus don't understand integer constants. You can simply use STD_LOGIC_VECTOR constants for the states or define an enumeration type for the state variable.

Generally, when you are using a particularly library, you should try to understand, which data types are supported by it.

To convert an integer to a std_logic_vector, you must specify if you intend a signed or unsigned representation.

I also don't see the purpose of using the bit_vector type in your code. std_logic_vector would be sufficient.