hamed_sotoudi
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Hi every body
I have designed a board using AD9265 according to datasheet and its evaluation board but when I sampled 140MHz single tone signal with 80 MHz sampling frequency I got 8.5 bit ENOB. Also I have used AD9524 clock distributor for low jitter clock. I compared my result with its figures in datasheet and considered that in its data noise floor is on -120db but noise floor in my data is about -80db. So whhat can be the problem in this system?
I have designed a board using AD9265 according to datasheet and its evaluation board but when I sampled 140MHz single tone signal with 80 MHz sampling frequency I got 8.5 bit ENOB. Also I have used AD9524 clock distributor for low jitter clock. I compared my result with its figures in datasheet and considered that in its data noise floor is on -120db but noise floor in my data is about -80db. So whhat can be the problem in this system?