Active HDL-Gate Level Simulation

[mangohaha]

Synplify pro finished the synthesis, output files are :
edf-design netlist in the format of the supported target place-and-route tool;
srs—output by the compiler stage of the process, contains the RTL
level (schematic) view of the design. This is the representation displayed
through the RTL view in HDL Analyst.

Which one should be used for the GLS on active HDL?

Thanks