try to use structural verilog... make code for multiplier first then connect all like this,,, :
module multiplier_fn(inp1,inp2,product);
input [31:0] inp1,inp2;
output [31:0] product;
assign product = inp1 * inp2;
endmodule
module activation_fn_2 (inp1,inp2,inp3,cin_low,cout1,out);
input [31:0] inp1;
input [31:0] inp2; //inp3=1/3
input [31:0] inp3; //inp3=1/15
input cin_low;
output [9:0] out;
output cout1,cout2;
wire [31:0] x1,x2,x3,x4;
wire [31:0] y1,y2,y3;
multiplier_fn G1 (.inp1(inp1),.inp2(inp1),.product(x1));
multiplier_fn G2 (.inp1(x1),.inp2(inp1),.product(x2));
multiplier_fn G3 (.inp1(x2),.inp2(inp2),.product(y1));
multiplier_fn G4 (.inp1(x2),.inp2(x1),.product(x4));
multiplier_fn G5 (.inp1(x4),.inp2(inp3),.product(y2));
full_subs_10bit G6 (.A(inp1),.B(y1),.cin1(cin_low),.c_out(cout1),.sum(y3)); // full substractor
rca_top G7 (.A(y3),.B(y2),.cin1(cin_low),.c_out(cout2),.sum(out)); //ripple carry adder
//im not sure how to feed inp2=1/3 and inp3=1/15,, maybe by use fixed point number for the testbench, please tell me then.
//please correct me if i do mistakes,,, thanks <faiz.omaq@gmail.com>