Actel SmartFusion simple VHDL example?

[farhada]

Hi,
Does anyone has a simple VHDL code for Actel's smartfusion eval board? Everything Actel give as examples are very large designs. I am looking for something very simple like toggle the LEDs or something,

Appreciate your help,
/Farhad

 

[cim123]

Hi Farhad,

I am also currently working on the smartfusion eval kit.
Why can't you just make your own design.

Take input as the switches and connect them to the leds, or have a counter which increments. Map the correct I/O.

Here is a sample in verilog.

module toggle_led(
clk,
rst_n,

sw1, // switch
led // 8 leds
);

input clk ;
input rst_n ;

input sw1 ;

output [7:0] led ;

reg [7:0] led_reg ;

assign led = led_reg ;

always @(posedge clk or negedge rst_n)
begin
if(!rst_n)
led_reg <= 8'h00 ;
else if(sw1)
led_reg <= led_reg + 8'h01 ;
end

endmodule

Map the clk, rst, sw1 and led to their proper i/o. haven't put any debouncing.

Regards
Manish

 

[farhada]

Hi thanks,
I can write the code myself, but smartfusion needs special clock input block and I thought someone has aldready got an example to show how to instantiate and use it.

I will see for myself then,

Thanks,
/Farhad

 

[yicheng]

farhada and cim123.Nice to meet you!I am Chinese.
I finded the smartfusion eval kit so long,but not on sale on China before July.
Do you think about smartfusion ?I used proasic3 and fusion for many project,they is good at single chip and security,they is suitable to games.

 

[cim123]

Hi,

Sorry for misinterpreting the question.
Regarding the clock management block, can you not instantiate it from the Catalog pane ?
I will try it today.

Hi Yi Cheng, nice to meet you too.
Yes the eval kit as around 4-8 weeks of lead time. What do you mean by suitable for games ? What kind of game console have you used them for ?

Regards
Manish

 

[yicheng]

Hi,
I had many large-scale games machine, PC is used as control centre,and used Actel's chip to implement the interface,protocol,maybe it is single chip,make our customer have a good feeling at their product's security.

 

[farhada]

Hi,

Sorry for misinterpreting the question.
Regarding the clock management block, can you not instantiate it from the Catalog pane ?
I will try it today.

I am afraid I can not find anything there, I only find a clock delay. This is really annoying Actel does not have a simple tutorial using simple VHDL code to do toggle LED for example.

 

[shitansh]

Hi farada,

the code you received for smart-fusion was originally developed by me for Fusion Embedded Development Kit and later they have edited it by their own and used for smart fusion.

For clock you need to used CLKINT buffer, means you need to pass your global signal to clock buffer i.e. clock and reset.

If you dont know how to use that you can download core library document. or do one thing make one test file for smart generator and instantiate CLK buffer from catalog window and then see its vhdl file in component directory which resides in your project directory.

perhaps this code may help you, although I always use verilog you need to check this for syntax.

-- TOP.vhd



library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;



entity TOP is

    port (clock     :   in  std_logic; 

          resetn    :   in  std_logic;

          led       :   out std_logic_vector(3 downto 1)

 );

 

end TOP;



architecture behav of TOP is


signal rst_n     : std_logic;
signal clk       : std_logic;
signal count     : std_logic_vector(27 downto 0);

--define clkint for board reset

--component clkint
component CLKINT

	port (a	: in std_logic;

	      y : out std_logic

	      );

end component;

--reset : clkint port map (resetn , rst_n);
reset : CLKINT port map (resetn , rst_n);
--clock : clkint port map (clock , clk);
clock : CLKINT port map (clock , clk);

counter: process(rst_n, clk)

    begin

        if (rst_n = '0') then

            count   <= x"0000000";

        elsif rising_edge(clk) then

            count    <= count + '1';

        end if;

end process counter;

led(1)  <= NOT(count(27));

led(2)  <= NOT(count(26));

led(3)  <= NOT(count(25));


end behav;

make assignment for clock, reset and led for smart fusion.
HTH,

 

[farhada]

Hi,
It doesn't work, I have to contact ACTEL FAE to see if it is even possible.

It seems like for SmartFusion if the clock is a crystal oscialtor, then I need to add the CCC and use the integrated ARM processor in the system.

Will see what I can do.

Cheers,
/Farhad

Added after 2 hours 32 minutes:

Solved the problem myself.

The SmartFusion unlike older ACTEL FPGAs has some limitation for crystal oscillator clocks.

You must add a MSS, configure the cloc the way you want to do, then add the connection on the top level between the MSS block and the custom VHDL code and then you are ready to go.

Not difficult after I figured it out, but it is not so easy when the documentation from ACTEL is not very clear on these items.