Accurate timing and voltage level during CPLD programing

[vaf20]

during CPLD programing

hi my friends
A basic question comes to my mind ....would anyone please tell me more about
accurate timing and voltage level during CPLD programming for all of pins included: IO+JTAG+VCCINT+VCCIO+GND

 

[farhada]

during CPLD programing

Hi,
IO is internally pulled up in normal cases (for Xilinx for sure) with a 100k ohm, so the voltage leve depends on how the CPLD pins are uses.

JTAG, you would be able to find the ifnromation easily on the datasheets.

VCCINT and VCCIO, are aso controlled by the user, it is your design and you should be able to ideintify the level, if everything is OK, you should not see any changes on them.

GND should be the same.

BR,
/Farhad

 

[vaf20]

Re: during CPLD programing

txn dear Farhad
i know , but i mean accurate timing and level ...suppose TDI in JTAG which bitstream file carry through it as u know, so there is voltage changing on TDI ...am i right ?...what about TCK or other pins?
tnx ahead

 

[farhada]

during CPLD programing

Dear Vaf20,
The level on the JTAG signals depends on the JTAG device you are using and how you power that device.

The frequency is also highly dependent on the JTAG device. I don't think you can say a general timing for all the devices.

I have some document about the relation between the different JTAG signals, I will send it as soon as I find it.

BR,
/Farhad