hi my friends
A basic question comes to my mind ....would anyone please tell me more about
accurate timing and voltage level during CPLD programming for all of pins included: IO+JTAG+VCCINT+VCCIO+GND
Hi,
IO is internally pulled up in normal cases (for Xilinx for sure) with a 100k ohm, so the voltage leve depends on how the CPLD pins are uses.
JTAG, you would be able to find the ifnromation easily on the datasheets.
VCCINT and VCCIO, are aso controlled by the user, it is your design and you should be able to ideintify the level, if everything is OK, you should not see any changes on them.
txn dear Farhad
i know , but i mean accurate timing and level ...suppose TDI in JTAG which bitstream file carry through it as u know, so there is voltage changing on TDI ...am i right ?...what about TCK or other pins?
tnx ahead