Accesss text File and Display it in FPGA

Hi all,

I want to read a set of data from a text file and show each data in every clock cycles. am using $readmemh function to read tha text file and store it in a register. But the problem is I can not show each element of that register in one clock cycle. Here is my code


module ppg_peak(clock,reset,show_val);

parameter DATA = 18;
input clock,reset;
output [27:0] show_val;


reg [27:0] show_val;
// Declare memory array that is twelve words of 32-bits each
reg [27:0] Mem [0ATA];

reg [DATA:0] k;
// Fill the memory with values taken from a data file
initial
begin
$readmemh("myfile_new.txt",Mem);
end

always@(posedge clock)
begin
if(reset <= 1)
begin
show_val <= 0;
k <= 0;
end
else
begin
if(k <= DATA)
begin
show_val <= Mem[k];
k <= k+1'b1;
end
else
k <= 0;
end
end

endmodule


Is there any other solutions for doing this? Moreover the text file can be accesed while I am using Modelsim but cannot be accessed in Quartus II with same code why??

Thanks in Advance.

What version of Quartus II are you using?

I was under the impression that Quartus would support Verilog $readmemh for synthesis, but I didn't try. Altera IP is however using altsyncram instances and it's init_file feature to implement initialized RAM/ROM. It's also working in Modelsim, if you are using *.hex rather than Altera specific *.mif files. There may be also an issue with different file locations expected by Quartus versus Modelsim.

FvM said:

I was under the impression that Quartus would support Verilog $readmemh for synthesis ...

Click to expand...

You are correct FvM, according to:

Reference "Altera 10.x Recommended HDL Coding Styles", pg 10-34, Section "Specifying Initial Memory Contents at Power-Up."

Altera 10.x Recommended HDL Coding Styles

Quartus II integrated synthesis and other synthesis tools also support the $readmemb
and $readmemh commands so that RAM initialization and ROM initialization work
identically in synthesis and simulation. Example 10–27 shows an initial block that
initializes an inferred RAM block using the $readmemb command.

Refer to the Verilog Language Reference Manual (LRM) 1364-2001 Section 17.2.8 or the
example in the Templates for the Quartus II software for details about the format of
the ram.txt file.

Example 10–27. Verilog HDL RAM Initialized with the readmemb Command
reg [7:0] ram[0:15];
initial
begin
$readmemb("ram.txt", ram);
end

Click to expand...

However, I have yet to dig up v9.x or earlier of this reference manual to verify $readmemh compatible with earlier versions of Quartus II.

$readmemb support for RAM inference is mentioned since V7.0 of the Quartus Software Handbook. So it should work.