About Xilinx Programming EPROM and Spartan 2 FPGA

[cssheu]

xilinx programming

Hello:

This is my first time to use Xilinx FPGA.

I had designed the PCB , now I want to test my code is correct,

so I have to program the code to the Xilinx EPROM .

I have question about programming , I upload my schematic about Xilinx FPGA programming circuit.

I use a XC18V01PC20 EPROM and a X2S150PQ208 Spartan 2 FPGA, between XC18V01PC20 and X2S150PQ208 I use Master-Serial Mode,
so I tired the M0, M1,M2 to the ground.

I use (JTAG) Master/Slave Mode from Xilinx download cable connecter through XC18V01PC20 to X2S150PQ208.

I never use the xilinx programming tools (impact),so I have no idear how to program the XC18V01PC20.

If you have the tech document files about xilinx programming tool, please share with me.

Thank you a lot.

 

[Bartart]

spartan 2 fpga

>>I upload my schematic about Xilinx FPGA programming circuit.

pdf file is corrupted

>>I use a XC18V01PC20 EPROM and a X2S150PQ208 Spartan 2 FPGA, >>between XC18V01PC20 and X2S150PQ208 I use Master-Serial Mode,
>>so I tired the M0, M1,M2 to the ground.

>>I use (JTAG) Master/Slave Mode from Xilinx download cable connecter >>through XC18V01PC20 to X2S150PQ208.

When the JTAG port is used to program the ISP PROM, the following steps must be taken:

· Using M0-M2 to set the Configuration Mode of the Spartan FPGA to Master Serial Mode.
· The Virtex-II FPGA is placed in the Bypass Mode in the Xilinx programming window. You will need to associate the FPGA with either a dummy .bit file or a .bsd file to allow the JTAG programming software to pass data through the FPGA.
· The design .mcs file is used to download the design into the 18V01 ISP PROM.
· Upon programming of the 18V01 ISP PROM, push PROGn button to initiate the Spartan FPGA configuration.

>>If you have the tech document files about xilinx programming tool, >>please share with me.

http://toolbox.x*l*nx.com/docsan/x*l*nx5/pdf/docs/pac/pac.pdf

Please upload schematic again,


Bart