about warning of vhdl!

[chxgzl4862]

warning:ngdbuild:452

hi everybody

my project

entity CLKDIV is
------------------------------------------
port (
CLK_IN : in std_logic;
CLK_RST: in std_logic;
CLK_CS : in std_logic;
CLK_NUM: in std_logic_vector ( 8 downto 0 );
CLK_OUT: out std_logic
);
------------------------------------------
end CLKDIV;

architecture Behavioral of CLKDIV is
------------------------------------------
signal CLK_CLK: std_logic;
signal CLK_CNT: std_logic_vector ( 8 downto 0 );
------------------------------------------
begin
------------------------------------------
div: process ( CLK_RST,CLK_IN,CLK_CS )
begin
if ( CLK_RST = '0' ) then
CLK_CLK <= '1';
CLK_CNT <= "000000000";
elsif ( CLK_IN' event and CLK_IN = '1' and CLK_CS = '0' ) then
CLK_CNT <= CLK_CNT + 1;
if ( CLK_CNT = CLK_NUM ) then
CLK_CLK <= not CLK_CLK;
CLK_CNT <= "000000000";
end if;
end if;
end process div;

CLK_OUT <= CLK_CLK;
------------------------------------------
end Behavioral;


entity IIC_CLK is
------------------------------------------
port (
IIC_CLKIN: in std_logic;
IIC_RST: in std_logic;
IIC_CS: in std_logic;
IIC_CLKOUT0: out std_logic;
IIC_CLKOUT1: out std_logic
);
------------------------------------------
end IIC_CLK;

architecture Behavioral of IIC_CLK is
------------------------------------------
component CLKDIV
port (
CLK_IN : in std_logic;
CLK_RST: in std_logic;
CLK_CS : in std_logic;
CLK_NUM: in std_logic_vector ( 8 downto 0 );
CLK_OUT: out std_logic
);
end component;
------------------------------------------
------------------------------------------
signal IICaaaaSampClk: std_logic;
signal IICaaaaClk: std_logic;
signal IICDivNum0: std_logic_vector ( 8 downto 0 );
signal IICDivNum1: std_logic_vector ( 8 downto 0 );
------------------------------------------
begin

IICDivNum0 <= "000000000";
IICDivNum1 <= "000000000";
IIC_CLKOUT0 <= IICaaaaSampClk;
IIC_CLKOUT1 <= IICaaaaClk;

I2C_SampClk: CLKDIV
port map (
CLK_IN => IIC_CLKIN,
CLK_RST => IIC_RST,
CLK_CS => IIC_CS,
CLK_NUM => IICDivNum0,
CLK_OUT => IICaaaaSampClk
);

IIC_Clk: CLKDIV
port map (
CLK_IN => IIC_CLKIN,
CLK_RST => IIC_RST,
CLK_CS => IIC_CS,
CLK_NUM => IICDivNum1,
CLK_OUT => IICaaaaClk
);

end Behavioral;

WARNING:Xst:1989 - Unit <IIC_CLK>: instances <I2C_SampClk>, <IIC_Clk> of unit <CLKDIV> are equivalent, second instance is removed
WARNING:NgdBuild:452 - logical net 'I2C_SampClk/CLK_NUM<0>' has no driver
WARNING:NgdBuild:452 - logical net 'I2C_SampClk/CLK_NUM<1>' has no driver
WARNING:NgdBuild:452 - logical net 'I2C_SampClk/CLK_NUM<2>' has no driver
WARNING:NgdBuild:452 - logical net 'I2C_SampClk/CLK_NUM<3>' has no driver
WARNING:NgdBuild:452 - logical net 'I2C_SampClk/CLK_NUM<4>' has no driver
WARNING:NgdBuild:452 - logical net 'I2C_SampClk/CLK_NUM<5>' has no driver
WARNING:NgdBuild:452 - logical net 'I2C_SampClk/CLK_NUM<6>' has no driver
WARNING:NgdBuild:452 - logical net 'I2C_SampClk/CLK_NUM<7>' has no driver
WARNING:NgdBuild:452 - logical net 'I2C_SampClk/CLK_NUM<8>' has no driver

why? ise 10.1 xinlinx xc95144

 

[thiagu_comp]

warning in vhdl

The only difference between both instances is CLK_NUM. But IICDivNum0 and IICDivNum1, both are assigned the same value of "0". This is the reason. The synthesize tool understand this as redundant logic.

One way to avoid this is - Not to assign "0" initially and make it as inputs.

Other way to avoid is - Assign different values.

Third way avoid is to use synthesis constraints - Set "Equivalent Register Removal" to "NO".

 

[chxgzl4862]

warning vhdl

thanks! i try it again!