about voltage or current in a large chip??

[tkevin73]

hello~
How do we distribute voltage or current references in a large chip?

 

[gevy]

Only current reference !
If lines is long that voltage reference is very inaccurate.

 

[sengyee88]

Only current reference !
If lines is long that voltage reference is very inaccurate.

Not truly agree.

If the path is long and carrying large reference current (unlikely case), yes, current reference is better, to avoid inaccuracy of voltage reference due to additional IR drop from metal resistance. But, the trade off is having this additional IR drop that may have headroom issue for low supply design. Anyway, it is weird that having large current flowing around the chip that heat up the whole IC.

I would preffer having a voltage reference at all time, if the path is long, try to reduce the current flowing through the path, by having local current amplification if needed.
For CMOS design, you may not have this issue, as most voltage references are biasing MOS gate, where MOS gate current is negligible.

For large chip, i will consider all MSP blocks (main signal paths) sharing the same voltage reference. Other individual blocks or non-matching critical blocks may share another seperate voltage reference, if the routing is indeed really far.

 

[Areky_qin]

Hi, sengyee88,
you have said,
For CMOS design, you may not have this issue, as most voltage references are biasing MOS gate, where MOS gate current is negligible.

If the path is long, IR drop is inevitably, at the same time, the vdd and gnd pad locations are limited too, the power drop is inevitably too, then how can we ensure the voltage reference accurate? maybe we can use the wider metal track to run reference signal track and power track, if the long path is longer than 10,000u? how to do?

Added after 2 minutes:

we have do such a case, opamp array are used to buffer output signal, the test results shows the output pins deviation is very large, more than 30mv.

 

[sengyee88]

Hi,

The discussion overhere is voltage or current reference. It is not power line or buffers that drawing significantly large current.

I think a typical voltage reference is derived from bandgap, IR drop on power line should not affect voltage reference accuracy, hence the term supply independant reference.

Let say your path is 10 mm, as you have suggested.
1. You provide a gate voltage reference (where gate current is really small) through this path.
2. You provide a current reference of 5uA through this path.

I think voltage reference will be much make sense, assuming same metal dimension.

opamp array are used to buffer output signal, the test results shows the output pins deviation is very large, more than 30mv.

If your output buffer is placed 10mm away from the pads, I think 30mV deviation is good enough. Have you tried to place the buffer as closed to pad as possible and make the reference as short as possible and the 30mV deviation gone? I doubt this is due to mismatch and finite gain of the opamp more than the opamp reference inaccuracy.