about this project of vhdl

[microcreater]

project of vhdl

hello everybody!
my project of vhdl
what's warning in it?
entity IIC_CLK is
------------------------------------------
port (
IIC_CLKIN: in std_logic;
IIC_RST: in std_logic;
IIC_CS: in std_logic;
IIC_NUM: in std_logic_vector ( 7 downto 0 );
IIC_CLKOUT0: out std_logic;
IIC_CLKOUT1: out std_logic;
IIC_CLKOUT2: out std_logic
);
------------------------------------------
end IIC_CLK;

architecture Behavioral of IIC_CLK is
------------------------------------------

component CLKDIV
generic ( reglong: integer );
port (
CLK_IN : in std_logic;
CLK_RST: in std_logic;
CLK_CS : in std_logic;
CLK_NUM: in std_logic_vector ( reglong downto 0 );
CLK_OUT: out std_logic
);
end component;
------------------------------------------
------------------------------------------
signal IICSampClk: std_logic;
signal IICStepClk: std_logic;
signal IICStep6xClk: std_logic;
signal IICDivNum: std_logic_vector ( 9 downto 0 );
------------------------------------------
begin

IIC_CLKOUT0 <= IICSampClk;
IIC_CLKOUT1 <= IICStepClk;
IIC_CLKOUT2 <= IICStep6xClk;

I2C_SampClk: CLKDIV
generic map( 3 )
port map (
CLK_IN => IIC_CLKIN,
CLK_RST => IIC_RST,
CLK_CS => IIC_CS,
CLK_NUM => IICDivNum ( 7 downto 4 ),
CLK_OUT => IICSampClk
);

IIC_Clk: CLKDIV
generic map( 3 )
port map (
CLK_IN => IICSampClk,
CLK_RST => IIC_RST,
CLK_CS => IIC_CS,
CLK_NUM => IICDivNum ( 3 downto 0 ),
CLK_OUT => IICStepClk
);

IIC_6xClk: CLKDIV
generic map( 1 )
port map (
CLK_IN => IICStepClk,
CLK_RST => IIC_RST,
CLK_CS => IIC_CS,
CLK_NUM => IICDivNum ( 9 downto 8 ),
CLK_OUT => IICStep6xClk
);

IIC_SCK:
process ( IIC_RST,IIC_CS,IIC_NUM )
begin
if ( IIC_RST = '0' ) then
IICDivNum <= "1111111111";
if ( IIC_CS = '0' ) then
IICDivNum ( 9 downto 0 ) <= "10" & IIC_NUM ( 7 downto 0 );
end if;
elsif ( IIC_RST = '1' and IIC_CS = '0' ) then
IICDivNum ( 9 downto 0 ) <= "10" & IIC_NUM ( 7 downto 0 );
else
IICDivNum <= "0000000000";
end if;
end process IIC_SCK;

end Behavioral;

 

[devas]

Hi,

It is easier for use to help you when you describe the warning message you get with your code and with which tool you get the message.

Devas

 

[microcreater]

hi,thans to your reply.
the tools is ise 10.1,cpld is xc95144.
this project have not warmning when i compile with ise 10.1.
but i want to know if there have any bug in it?

 

[devas]

Hi,

When you do not get any warning/error messages when you compile it with ISE than you can assume that the VHDL code is syntactically correct.

When you want to know if the VHDL code behaves like you intend, you can simulate it. ISE has a simulator that I am not familiar with. Otherwise you can download Modelsim Xilinx edition from the Xilinx web-site for free and use this simulator to simulate the VHDL code.

Success,

Devas