about the usage of the VHDL libraries

[lahrach]

about VHDL

hello all,

somme times some vhdl codes are written without libraries like

ntity b01 is
port(
line1: in bit;
end b01;

architecture BEHAV of b01 is

end BEHAV;

someone can explain me why it is not necesary to writre

library ieee;
use ieee.std_logic_1164.all;

thanks again

 

[Maxwell077]

Re: about VHDL

Libraries include some definitions, primitives, data types, arithmetic and some other functions...
If libraries is not defined in your VHDL codes, you'll have problems while using them..

Usually, libraries come directly to top of code file by default.... it's enough most of time...

 

[devas]

Re: about VHDL

Hi,

In your example the type that is used is "bit". This is an internal defined type in VHDL. As soon as you use std_(u)logic, unsigned, etc, you need to use the std_logic_1164 library that defines these types. The use of bit-type is limited and not used very much. Mostly std_logic is used.

Devas

 

[edrin_88]

Re: about VHDL

actually if u are dealing with inly (0,1) then BIT format is enough.
for any designs in vhdl u need 3 libraries called (IEEE,WORK,STD).From this WORK AND STD IS default.you rBIT comes under STD library which is default.
So you can define without library declaration.



is that clear?


edrin

 

[Maxwell077]

Re: about VHDL

Dear edrin,
To mimic most of hardwares', 2-state types are not enough.. Please remember that, VHDL is used for hardware description.. So, most of time, 8-state values are used..

Ilgaz

 

[lahrach]

hi

but there is only three states which are synthetezable( 0.1.z)

isn't it

 

[amithsanu]

hello... In vhdl library, Is there any option for complex multiplications?? i mean handling complex values????