Hi,
Yes. You are right. First flop may go in metastable condition. In this case, output will be unpredictable, it might be oscillating between some voltage levels, or it might be moving to some voltage level( i.e. either Vcc or Vss).
While one use the synchronizer, one has to make sure that the first flip flop will resolved to some value(it can resolve to either 0 or 1) before the clk edge to second flop. i.e. for the first flop it has 1 clk period to get resolved. If this doesn't happen and metastable state of FF1, persist even after clk period time, second FF will either sample it inappropriately or second FF may also go in metastable. But in practice the chance of going second FF in metastable is very very less.(depends on MTBF of synchronizer).
One should make design by keeping in mind that synchronizer is going to take 2 clk cycles to transfer the value of other clk domain faithfully.
I hope this will help you.