About the layout of Power Supply

[Chung Chun Chen]

have a question about the layout considerations of power supply (3.3v).

Do you know any reference of it?

I don't know how to consider it.

For example, which metal is suitable as the wire of power supply?

How does I consider the pad of power supply such as size, placement?

Thank you for your help

 

[flatulent]

Once you select the conductor (trace) size to maximize efficiency within economic considerations, EMI is the next big concern. Current carrying loops should be made as small as possible.

 

[tsanlee]

In some design rule ,the current density of Metal is 1mA/1um. the resistor in top metal is better than bottom one.

About the I/O pad , you can contact your package house. ( the bonding wire diameter )

 

[justin999]

top several metal always used as power wire

 

[huojinsi]

1. About the wire of power supply,u can calculate metal width by foundry process
parameter (metal density).
2. About the pad size of power supply, the package house may give u a
reference.At the same time, u must consider the current capacity and adjust
your pad size.
About the pad position of power supply, u can place it according to requirements
of layout and package.

 

[kapils1982]

Always the topmost metal is used for power routing

 

[uncle_urfi]

You use top metal (b/c of least resistance).

Let's say that the top metal is M5; you can setup the power routing such that M5, M3 and M1 are the vdd and M4, M2 are the ground going to the pad. so that they also act like a decoupling capacitor. Most people don't like to spend time doing this.

Another important consideration is how you slot the power supply lines; and there should absolutely be no 90 deg turns on the main connection going to the pads, as this would cause electron migration for higher current levels. The direction of the slotting is 'as' important as the slotting itself.

Heavy decoupling using fractals has been reported. check 'fractal capacitors' on the Xplore. The fractals can fill all available space. You can use small unit capacitors and place them manually. don't short vdd and vss!!

About the pads; you usually use the same sized pads, but separate the digital and the analog and the buffer supplies. Even so, if you require more current, then you use mulitple pads in parallel. This techniques is well-known for power amplifier layouts. A typical 70 um x 70 um pad in a submicron technology can carry 200 to 300mA quite easily but i would not push these so far without an expert doing my layout. For a digital chip, if you want to shove in 5A, you should have multiple VDDs and multiple VSSs on chip. This is the whole idea of the flip-chip package movement; localized supplies.

The power routing should follow a tree-structure, or a comb-structure or a combination thereof. Don't use a chain-structure, or else vdd drops would result.

While simulating, did you use any filters on the supply or was it just a dangling 'vdc' from the analogLib?