about the case statement in verilog

[swasiki]

hi guys,
I'm just studying the verilog, and got something very wired in case statement. The followings are the code, and it's very simple:

always @(*)
	begin
		casex({aluop_ex, funct})
			6'b000??? : alu_ctrl <= 0000;
			6'b010000 : alu_ctrl <= 0000;
			6'b010001 : alu_ctrl <= 0001;
			6'b010010 : alu_ctrl <= 0010;
			6'b010011 : alu_ctrl <= 0011;
			6'b010100 : alu_ctrl <= 0100;
			6'b010101 : alu_ctrl <= 0101;
			6'b010110 : alu_ctrl <= 0110;
			6'b010111 : alu_ctrl <= 0111;
			6'b011000 : alu_ctrl <= 1000;
			6'b011001 : alu_ctrl <= 1001;
			6'b100??? : alu_ctrl <= 1010;
			6'b110??? : alu_ctrl <= 1011;
			6'b111??? : alu_ctrl <= 1100;
			default 	 : alu_ctrl <= 1111;
		endcase
	end

The result in ISim simulator is as follows:

0alu_ctrl=0000
                  20alu_ctrl=0001
                  [B]30alu_ctrl=1010
                  40alu_ctrl=1011[/B]
                  50alu_ctrl=0100
                  60alu_ctrl=0101
                  [B]70alu_ctrl=1110
                  80alu_ctrl=1111[/B]
                  90alu_ctrl=1000
                 100alu_ctrl=0010
                 110alu_ctrl=0111
                 120alu_ctrl=0011
                 130alu_ctrl=1100

The wired result happens at 30ns alu_ctrl =1010, which should be 0010, and the same wired result came at 40ns, 70ns, and 80ns
I can not figure out why. At first I thought this might be a bug in the statement, but after I use iverlog, I got the same result, so it might be something wrong with my code.
can someone please help~~~?
Thanks very much

 

[hartejpal]

How are aluop_ex and funct changing?
Can you attach your complete code and the test bench code?

It is difficult to assess without that.