about the cap match accuracy in pipelined adc

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didibabawu

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We know that in pipeline ADC the cap match accuracy is very important for resolution of 10bit and below. I have done some simulation about the cap mismatch using monte carlo analysis. My result is the 10 bit needs cap mismatch lower than 0.12%. I dont know whether the result is right. Can any body give me the answer?
thx.
 


I think something is wrong now, but can anyone give me your answer?
 

you can check it by yourself. the mismatch caused error should be less than 1/4 LSB voltage.
 

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    didibabawu

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noiseless said:
you can check it by yourself. the mismatch caused error should be less than 1/4 LSB voltage.
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Thank you very much. But I want to know why 1/4LSB not 1/2LSB.
 

Hi
as I know, all errors such as mismatch, settling, gain error and ...
must be less than 1 LSB.
regards
 

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