Library IEEE;
Use IEEE.std_logic_1164.all;
Use IEEE.std_logic_arith.all;
Use std.textio.all;
Entity Test01 is
Port( clk : in std_logic;
reset : in std_logic;
string_in : in character;
ABC : out std_logic);
End Test01;
Architecture a of Test01 is
type state_type is (idle, ss, s0, s1, s2, s3);
signal state, next_state :state_type;
Begin
change_state: Process(reset, clk)
Begin
if reset = '1' then --reset system
state <= idle;
elsif (rising_edge(clk)) then
state <= next_state; --update state on clock
if (state = s3) then
ABC <= '1';
else
ABC <= '0';
end if;
end if;
end process change_state;
process_bit: Process(state, string_in)
Begin
case state is
when idle =>
next_state <= ss;
when ss =>
next_state <= s0;
when s0 =>
if (string_in='A') or (string_in='a')then
next_state <= s1;
else
next_state <= ss;
end if;
when s1 =>
if (string_in='B') or (string_in='b')then
next_state <= s2;
else
next_state <= ss;
end if;
when s2 =>
if (string_in='C') or (string_in='c') then
next_state <= s3;
else
next_state <= ss;
end if;
when s3 =>
next_state <= s3;
end case;
END process process_bit;
End a;