jedihe,
If we are talking about synthesis, you are correct.
Because <= is used, the first line in the process defines a DEFAULT, not an initialization. And the following lines with <= represent overriding definitions of the signal.
If := were used, logic would need to be created that generates a result equivalent to a sequential execution with delayed results.
As far as I know, asynchronous digital computers are still pretty much research objects. One must remember that conventional computer architecture is CLOCKED LOGIC. Software programming assumes this, even though the granularity of the clocking may be unknown or ignored.
If the process were truly executing sequentially, what is clocking it? And if the process were truly executing sequentially, you would get a signal glitch when the example signal is set to 0 at the beginning of the process.
Finally, as a counterexample to "it's sequential", the following code represents a shift register, not a bit propagator:
Code:
process (clk)
begin
if rising_edge(clk) then
s3 <= s4;
s2 <= s3;
s1 <= s2;
s0 <= s1;
end if;
end process;