I think 200uV is exceptionally small - just my opinion, but very nice work.
As for the order of the mirrors, I think you will see some improvement if you try this.
VDD
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UP signal controlled Switch (PMOS)
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PMOS current mirror
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Vcontrol node
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NMOS current mirror
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DOWN signal controlled Switch (NMOS)
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GND
Because when you flip one of the switches, you need to charge/discharge the miller capacitanceas the gate switches from 0v to Vcc. Since CONTROL node is pretty high impedance, even a small burst of current gives a voltage spike. Putting the switches UNDER the mirrors as I show above means that miller cap discharges into the mirror's SOURCE, which is considered low impedance. Therefore no gain due to the low Rout seen and no voltage spike. The current mirror does a pretty good job of reducing the glitch that actually passes through to CONTROL node.
In order to get the biasing right, your current mirrors need a biasing strand like the one I show below. I show this as one big strand with a current source in the middle, but practically, you will probably use two strands, one for NMOS one for PMOS. I'm sure you know this, but some may not..
VDD
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A PMOS the same size as your switch device, with it's gate always tied to GND
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PMOS current mirror, diode connected
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Current source
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NMOS current mirror, diode connected
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An NMOS the same size as your switch device, with it's gate always tied to VCC
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GND
Now when your switch is on, it's Vdsat is matched to the Vdsat of the dummy device, and the mirror turns on with no offset voltage. If you do this, AND use an amp to control the mirrors, the effective impedance of the mirror's SOURCE will be reduced by the gain of the loop. I am guessing that this very low impedance will not glitch at all. Try it, and let me know what you think!