About PLL VCO control voltage and Charge Pump current ripple

[Analog_starter]

pll design, steering voltage circuit

Hi all,

I find there is ripple about 0.2mv P-P on the VCO control voltage ripple when my PLL locked in the simulation. How can I reduce it or it is small enough so I can ignore it?

Another question, I want to reduce the ripple of the Charge Pump current when the switch on/off because I think it will bring the mismatch between UP and DOWN the Vcontrol. I try to add large Cap on the gate of current mirror, but it seems no use. Who can tell me how to solve this issue?

Thanks.

Best Regards,
Analog_starter

 

[amarnath]

charge pump vco

pump current mismatch,has been an issue of research,many ieee papers address this issue.u can make a search of ieee papers,u can find it.

regards
amarnath

 

[electronrancher]

current steering charge pump

first - 200uV is exceptional! you can only hope that your chip has less than a few mV of ripple. try to look at it in terms of percent, and keep the percent lower than 1%... or 0.1% for extremely high accuracy.

say your full scale voltage in lock is 0.5v, you can endure 5mV steady state ripple before you reach the 1% region. and if your flip flop is giving ANY gate signal (either up or down) i think a few mV is as close as you're going to get without a huge RC and long lock times.

i made a 1MHz pll that locked in less than 100 cycles, and the ripple on that guy was about 10% - not a big deal for my application though since it was indeed locked.

second, i hope you are putting your switching devices UNDER your current mirrors, that's the only way to reduce noise because else you are fighting the miller capacitance. if switches are under the mirrors then the miller cap feeds into a low-impedance source greatly reducing the switch glitch. try a cascode, plus a switching device on the bottom (like a triple cascode in a way) to get very quiet transitions but it costs voltage headroom.

note that if you are putting switches under a mirror, the diode connected device needs a dummy switch whose gate is tied to vcc (for nmos) or gnd (for pmos)

one last thing - in order to equalize the capacitance of nmos and pmos (equalize glitch), sometimes you have to oversize nmos or undersize pmos as their kp is obviously different. in essence, big pmos and small nmos mirrors give an "offset" since pmos capacitance (and glitch) is 2x-3x bigger.

word..

 

[Analog_starter]

vco pump up

Hi,

The ripple of VCO control voltage in my case is 0.2mv, you mean it exceptional
big or exceptional small? My PLL locked at 700mv, the ripple/Vcontrol is about 0.03%.

For the latter of your reply, I can't make it clearly. What's the meaning of "putting your switching devices UNDER your current mirrors"? My Charge pump is the structure as below:

VDD
|
PMOS current mirror
|
UP signal controlled Switch
|
Vcontrol node
|
DOWN signal controlled Switch
|
NMOS current mirror
|
GND


Best Regards,
Analog_starter

 

[eng_Semi]

charge pump low inpedance

I find there is ripple about 0.2mv P-P on the VCO control voltage ripple when my PLL locked in the simulation. How can I reduce it or it is small enough so I can ignore it?

The ripples on the control voltage of the VCO will cause reference spurs, in the VCO spectrum, but according to the specs u wanna meet these ripples amplitude may be accepted or not. I mean that u must return to the standards of the application for which u r building ur PLL.

Another question, I want to reduce the ripple of the Charge Pump current when the switch on/off because I think it will bring the mismatch between UP and DOWN the Vcontrol. I try to add large Cap on the gate of current mirror, but it seems no use. Who can tell me how to solve this issue?

I think that u may try the current mode logic charge pump which depend on current steering and same mirrors for the UP and DN currents.

But U shouldn't optimize unless ur output don't meet ur specs

 

[Analog_starter]

vcxo charge pump

Hi,

But how can I know my PLL can meet the spec? The
results of simulation is so ideal comparing with the
actual one. So I just can do the best optimize, right?

Thanks.

Best Regards,
Analog_starter

 

[jotamario]

charge pump current mismatch in pll

Hi. analog_starter.

I designed a CMOS pll frequecy synthesizer and in my first design I had this same problem. The reason is that when you turn off for example the upper switch (suppose you use a PMOS switch) the source tha before was connected to Vcontrol now is connected to VDD. When you turn on this switch again your circuit is going to present a glitch due to load redistribution between the source of PMOS switch and Vcontrol node. This explanation is similar for the lower sitwch (NMOS).
The most practical solution is to make a feedback between Vcontrol and sources of upper switch (pmos) or lower switch (nmos) using a buffer (voltage follower).

Have you understood?

 

[Analog_starter]

vco charge pump

Hi,

Yes, I know that and I have already used an unit gain op for tracing the Vcontrol.
But this way can not reduce the ripple of the current when the switch ON/OFF.
It only can tracing the voltage.

Thanks.

Best Regards
Analog_starter

 

[electronrancher]

charge pump vco control

I think 200uV is exceptionally small - just my opinion, but very nice work.

As for the order of the mirrors, I think you will see some improvement if you try this.

VDD
|
UP signal controlled Switch (PMOS)
|
PMOS current mirror
|
Vcontrol node
|
NMOS current mirror
|
DOWN signal controlled Switch (NMOS)
|
GND

Because when you flip one of the switches, you need to charge/discharge the miller capacitanceas the gate switches from 0v to Vcc. Since CONTROL node is pretty high impedance, even a small burst of current gives a voltage spike. Putting the switches UNDER the mirrors as I show above means that miller cap discharges into the mirror's SOURCE, which is considered low impedance. Therefore no gain due to the low Rout seen and no voltage spike. The current mirror does a pretty good job of reducing the glitch that actually passes through to CONTROL node.

In order to get the biasing right, your current mirrors need a biasing strand like the one I show below. I show this as one big strand with a current source in the middle, but practically, you will probably use two strands, one for NMOS one for PMOS. I'm sure you know this, but some may not..

VDD
|
A PMOS the same size as your switch device, with it's gate always tied to GND
|
PMOS current mirror, diode connected
|
Current source
|
NMOS current mirror, diode connected
|
An NMOS the same size as your switch device, with it's gate always tied to VCC
|
GND

Now when your switch is on, it's Vdsat is matched to the Vdsat of the dummy device, and the mirror turns on with no offset voltage. If you do this, AND use an amp to control the mirrors, the effective impedance of the mirror's SOURCE will be reduced by the gain of the loop. I am guessing that this very low impedance will not glitch at all. Try it, and let me know what you think!

 

[Analog_starter]

vco control voltage

Hi electronrancher,

Thank you.
I will try it.

Best Regards
Analog_starter

 

[mmohsen]

vco op amp

about the current ripples or (glitches) from my practical experence i tried to decrease these glitches by trying to optimize the timing mismatch between (UP and UPB ,DN and DNB) signals so , when you are simulating ur PLL try to deal with PFD/CP as one block , try to use a chain of inverters in the control signals path in order to elminate this mismatch ,
and i think you would use current steering topologies in order to have less glitches on supply current .
while talking about mismatch which comes from switching i think using the unity gain op amp will help beside using cascode current mirrors.
regards

Added after 24 minutes:

I think 200uV is exceptionally small - just my opinion, but very nice work.

As for the order of the mirrors, I think you will see some improvement if you try this.

VDD
|
UP signal controlled Switch (PMOS)
|
PMOS current mirror
|
Vcontrol node
|
NMOS current mirror
|
DOWN signal controlled Switch (NMOS)
|
GND

Because when you flip one of the switches, you need to charge/discharge the miller capacitanceas the gate switches from 0v to Vcc. Since CONTROL node is pretty high impedance, even a small burst of current gives a voltage spike. Putting the switches UNDER the mirrors as I show above means that miller cap discharges into the mirror's SOURCE, which is considered low impedance. Therefore no gain due to the low Rout seen and no voltage spike. The current mirror does a pretty good job of reducing the glitch that actually passes through to CONTROL node.

In order to get the biasing right, your current mirrors need a biasing strand like the one I show below. I show this as one big strand with a current source in the middle, but practically, you will probably use two strands, one for NMOS one for PMOS. I'm sure you know this, but some may not..

VDD
|
A PMOS the same size as your switch device, with it's gate always tied to GND
|
PMOS current mirror, diode connected
|
Current source
|
NMOS current mirror, diode connected
|
An NMOS the same size as your switch device, with it's gate always tied to VCC
|
GND

Now when your switch is on, it's Vdsat is matched to the Vdsat of the dummy device, and the mirror turns on with no offset voltage. If you do this, AND use an amp to control the mirrors, the effective impedance of the mirror's SOURCE will be reduced by the gain of the loop. I am guessing that this very low impedance will not glitch at all. Try it, and let me know what you think!

i think you could simply say switching at source technique

am I right ??

 

[Analog_starter]

how to ignore small voltage spikes

Hi mmohsen,

Could you post full of this paper? Or send it to me?

Thanks.

Best Regards
Analog_starter

 

[sonnyasu]

hi do you guys know how high the bandwidth of the unity gain buffer should be? say the input is ranging from 2MHz to 16MHz, what is the bandwidth of your unity gain buffer?