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About P89C669 Microcontroller

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shashavali_m

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Hi all,
Can u give me some reference design for P89c669.
I want to know how to interface 8MB data memory.
Please give some tips as well as reference design.

Thanx in advance
 

silvio

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Hmmm, seems P89LPC924 it's a little bit overwhelming for you.
https://www.edaboard.com/ftopic147243.html

How about the chalenge of fitting 8MB code and data.

If I were you, I've been looking first to the software able to compile my program wrote for 51MX Philips Architecture.
Otherwise all features that follows are useless : the stack pointer extended to 16 bits (resides in EDATA if ESMM=1), the new 23-bit extended data pointer EPTR (EPH, EPM and EPL for indirect access to HDATA space 7E:FFFF)
and two 24-bit universal pointers PR0 and PR1 in order to access all of the various memory spaces in single unified manner (with EMOV instruction).

Read first the 51MX Architecture Reference and Instruction Set http://www.keil.com/dd/docs/datashts/philips/51mx_arch_ism.pdf
then choose the assembler or compiler and finnaly look after the 8MB SRAM / FLASH.

In order to ensure proper matching between the microcontroller and external device the following must meat.
As shown in data sheet, the program memory (typically EPROM or flash memory) interfaces to the processor's LSB address through the address demultiplexing latch. The EPROM also interfaces directly with the processor via the MSB address bus and the Program Store ENable (/PSEN\) signal.
Note that when 23-bit address is used, address bits A16-A22 will be outputted to
P2.0-P2.6 when ALE is HIGH, and address bits A8-A14 are outputted to
P2.0-P2.6 when ALE is LOW. Address bit A15 is outputted on P2.7 regardless of ALE.

Upon evaluation of the timing specifications for the processor, the latch and the EPROM, it can be seen that the most critical timing path is through the LSB address bus. The address must appear on this bus, pass through the latch, address the EPROM, and the EPROM must output valid data in less time than the CPU parameter tAVIV.
Since the latch is in the path, the timing of this bus can be expressed by the following equation: tPROP + tACC < tAVIV. The P89C669 data sheet shows that tAVIV is a function of clock speed (denoted tCLCL), and is given by: tAVIV = 2.5tCLCL - 30 ns. Solving these equations for 24 MHz operation using an F type latch (tPROP = 8 ns), it can be seen that an EPROM access time of less than 66 ns is required. Thish illustrates that the latch speed directly impacts the required speed of the EPROM (for HC type latch tPROP is 38 ns).
Things goes worst if we plan to use the full 23-bit Extended Addresing Mode. Just because the parameter that counts is now tAVIV1 (Address (A16-A22) to valid instruction in = 1.5tCLCL - 34 ns) which means an EPROM (FLASH) access time of less than 28 ns is required.

Regarding the data SRAM, it can be determined that 4 timing parameters are necessary and sufficient to meet the processor's timing requirements for most situations.
During a data read operation, the processor expects the time from an address change until valid data is available to be 157 ns (tAVDV= 4.5tCLCL - 30 ns) or less. If the propagation delay from D to Q of an F373 latch (8 ns) is subtracted from this parameter, you obtain a memory address access (tAA) requirement of 149 ns (or 119 ns using HC latch). Also for a data read operation, the time from the /RD signal going low until valid data is received from the memory device
must be 64 ns (tRLDV = 2.5tCLCL - 40 ns) or less. Since the processor's /RD signal is tied to the memory's /OE pin, the memory must have an output enable access time (tOE) of less than 64 ns. After the processor has read the data,
the SRAM must relinquish the bus within 26 ns (tRHDZ = tCLCL - 15). This dictates that the SRAM parameter tOHZ be less than 26 ns. For a write, the processor will provide a minimum write pulse of 9 ns (tWLWH = 0.5tCLCL - 11), which is equal to the minimum required write pulse width (tWP) of the SRAM.

Using the full 23-bit Extended Addresing Mode the processor expects the time from an address change until valid data is available to be 110 ns (tAVDV1= 3.5tCLCL - 35) or less.
If the propagation delay from D to Q of an HC373 latch (38 ns) is subtracted from this parameter, you obtain a memory address access (tAA) requirement of 72 ns.
 

shashavali_m

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Thanx for more information.
Please i need some reference design.How to do ISP.
Help me.
 

silvio

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shashavali_m said:
How to do ISP.
The In-System Programming (ISP) is performed without removing the microcontroller from the system through the UART0 serial interface of the P89C669. Not UART1 !!
You need this software: http://www.esacademy.com/software/flashmagic/FlashMagic.exe
You can read more about it : http://www.esacademy.com/software/flashmagic/fmfree.htm

The ISP of P89C669 is done through the internal bootloader. This can be invoked software if the Status Byte is set to a non zero value or hardware (see bellow).
At the falling edge of reset, the P89C669 examines the contents of the Status Byte. If the Status Byte is set to zero, power-up execution starts at location 00:0000H, which is the normal start address of the user's application code.
When the Status Byte is set to a value other than zero (in software), the 16-bits BootVector is used, factory programmed at 00:FC00 (BVH=00h for address A22:A16,BVM=FCH for address A15:A8 and low byte A7:A0 set to 00H)

You can invoke the bootloader by hardware like having a non-zero Status Byte. This is done by holding PSEN LOW, EA greater than VIH (usualy is tied to +5V in your application to force the micro executing from internal FLASH) and ALE HIGH at the falling edge of RESET.
This can be done manual with switches or jumpers or allow the FlashMagic performing automaticaly according to the page 41 of the manual you can read in the Help menu of the application.
Look carefully at the page 41. You still need the RS232 transceiver (standard MAX232).
 

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