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About low vt Mosfet in RF CMOS Process

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Newbie level 6
Nov 10, 2005
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native vt cmos

hello everyone.
now i got a RF CMOS process PDK, there are 4 types RF MOSFET: nominal vt, low vt, zero vt, and native vt. but i don't know what differences are there among these MOSFETs, especially between the nominal vt Mosfet and the latter 3 Mosfet. so anybody can help to explain them or give me some references?
thanks a million.

vt implant in cmos

the nominal vt transistor is transistor with vt like the logic process

the low vt transistor is transistor with low vt "usually they dope the substare of this tarnsistor to controll the vt

the zero vt , is the transitor depletion mode

but i donot know the native one

wish this help


Basically during fabrication you cant precisely control the subsrate doping , due to this there might be shift in Vt.

And hence Different kinds of Vt arises. Fabs gives models for transistors for all the
situation that can be encountered.

For Rf CMOS. if speed is the criteria then you need to the reach the specifications in high Vt process, as this the slowest of all. And if low power is the blocking criteria then you need to reach the spec in Low Vt process.

Definitions of the different Vt you asked for is as said by before post.

In my opinion, Native Vt is similar to nominal Vt process.


Thanks Khouly & pthoppay.

i have another question, that is, how to realize the low vt mosfet in process. i had searched in google and IEEE paper database, but can't find some valuable imformations. in the RF CMOS PDK, the low vt mosfet add an extra process step: the low vt implant, shown in figure below, but i donot know the effect of this process step. so who can tell me?

Hi ,
actually i too have a few doubts reg this , i will tell u what i know.
Vt decides two factors cheifly power and speed..

Low Vt devices have high inherent speed but high leakage power consumption..
The viceversa for high Vt.

But nominal Vt devices bridge both.

They effectively trade of between power and speed.

they 25 % faster than high vt but consume 10 % more power.. and so on..

i will soon upload a pdf xplaining this.


The effect of the process step is,

basically as the name suggests low Vt is having lesser Vt than the normal one.

This is can be acheived by various means( gate oxide thinkness, dielectric constant of gate oxide, doping concentration etc)

The easiest way to model low Vt is having less substrate doping.

Henec, if you see the diagram you have low Vt implant layer which means the subrstrate dpoing is less.


thanks for khouly, pthoppay, Resistance, and electronics_kumar.

Thanks for your reply and they are really helpful !

The native Vt is similar to Zero Vt in my opinion. In TSMC18, we can have Normal, Medium, and Native Vt.

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