verilog inout
Hi!
I'm unfamiliar with verilog so this is my simple question.
my netlist has some inout ports that must function as in ports (but i can't change them) so i've to add a tristate buffer. My code is similar to this:
module top(a,b,c,enable)
input enable;
inout a;
inout b;
output c;
if (enable=='0') begin
a<='Z'
b<='Z'
end
end module
I get this error on ncsim: a net is not a legal lvalue in this context [9.3.1(IEEE)]
I also tried assign and = but it didn't work.
What's wrong?
Thanks.