Hi...,
you have two questions.
1. how can i fix the contention?
During test logic insertion itself you should take care of contentions. Verify the three-state buses, bidi buses, bus holders in the design. if memories are present, check the memory outpt state.
Or u can ignore generating the patterns if it doesn't effect the coverage. But it is always beter to fix it.
2. how can i find the ID=481 gate?
It is purely tool dependent. Follow the tool related commands to back trace from the failed the gate. By the way, which tool r u using?
Added after 9 minutes:
Hi...,
you have two questions.
1. how can i fix the contention?
During test logic insertion itself you should take care of contentions. Verify the three-state buses, bidi buses, bus holders in the design. if memories are present, check the memory outpt state.
Or u can ignore generating the patterns if it doesn't effect the coverage. But it is always beter to fix it.
2. how can i find the ID=481 gate?
It is purely tool dependent. Follow the tool related commands to back trace from the failed the gate. By the way, which tool r u using?