About break down voltage of NMOS

[tia_design]

snapback voltage

In the process specification, the NMOS breakdown voltage is 7V. Testing case is that NMOS length is 0.6uM, gate, source and substrate are connected to ground, then sweep drain voltage till drain take 1uA current. Process supply is 5V

In my design, I have to take care of protection if op amp's output is accidentally connected to 16V or -6V. If I use NMOS with length of 1.2uM will the breakdown voltage be doubled? Normally how should I do in my design to take care above mentiion 16V and -6V cases. Thanks!

 

[oermens]

nmos breakdown

approximation is vbox=10^9*tox, so if your oxide thickness is 4nm, the breakdown voltage is approximately 4V

 

[snafflekid]

snapback breakdown

In the process specification, the NMOS breakdown voltage is 7V.

I think you are referring to snapback voltage, not oxide breakdown voltage?

The snapback voltage is affected by the impact ionization occurring in the drain region. A lightly doped drain lowers the impact ionization and raises the snapback voltage. Gate length has very little effect.

 

[erikl]

snapback voltage gate length

In my design, I have to take care of protection if op amp's output is accidentally connected to 16V or -6V. If I use NMOS with length of 1.2uM will the breakdown voltage be doubled?

No!

Normally how should I do in my design to take care above mentioned 16V and -6V cases. Thanks!

IMHO you can achieve this only by a protection scheme, which normally is used for inputs:

Unfortunately, by this you have to sacrifice the low output impedance of the OpAmp.
Probably you can omit R1 (protection diodes directly at the OpAmp output) and decrease R2
- if necessary - as long as R2, D1, D2 and the accidentally connected 16V or -6V sources can stand it.

 

[oermens]

breakdown voltage nmos

use esd protection cells and i/o pads from your foundry. it should be in your pdk