First question, do you know the meaning of the concatenation operator {x,y,z} in Verilog? It's simply assembling single bits or bit vectors to a result bit vector.
sum5 is adding the original D2 vector and a right shifted D2 value. The right shift is performed by omitting one LSB and adding the MSB for sign extension. Assuming D2 is a signed entity, you get sum5 = 1.5*D2.
sum6 is applying further calculations, tyr to figure it out.
You should take a closer look at {D2[23],D2[23:1]}. The operation is called arithmetic shift right. The bitvector is shifted right by omitting the least significant bit D2[0]. Arithmetic shift means, that the sign bit (most significant bit D2[23]) is duplicated. Examples for 4 bit signed numbers: