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# a verilog syntax help

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#### noura7

##### Member level 2

assign sum5=D2 + {D2[23],D2[23:1]};
assign sum6={D1[22:0],D1[0]} + {D3[23],D3[23:1]} +sum5;
assign sum7=sum6[23:19] + 1'b1;

tkx a lot
Noura

First question, do you know the meaning of the concatenation operator {x,y,z} in Verilog? It's simply assembling single bits or bit vectors to a result bit vector.

sum5 is adding the original D2 vector and a right shifted D2 value. The right shift is performed by omitting one LSB and adding the MSB for sign extension. Assuming D2 is a signed entity, you get sum5 = 1.5*D2.

sum6 is applying further calculations, tyr to figure it out.

thank you FvM for your response. Really i don't understand how can u get sum5=1.5*D2. Can you please give me further détails with examples

Thks a lot
Noura

You should take a closer look at {D2[23],D2[23:1]}. The operation is called arithmetic shift right. The bitvector is shifted right by omitting the least significant bit D2[0]. Arithmetic shift means, that the sign bit (most significant bit D2[23]) is duplicated. Examples for 4 bit signed numbers:

+4 ('0100') -> +2 ('0010')
-6 ('1010') -> -3 ('1101')

Summing D2 and 0.5*D2 results in 1.5*D2

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