msdarvishi
Full Member level 4
An strange error message : ERROR:Anno:169
Hello,
I encountered an strange error during the post-place and route simulation of my design that I would like to share it here for a possible solution.
I have a design that one of its parts is operating at high frequency and the rest at low frequency.
I used the IBUFG buffer to buffer the input clock signal and the output of this IBUFG buffer goes to:
1. A PLL to generate a higher frequency
and
2. directly connected to the clock input of the module that is operating at low frequency.
Then I synthesized, translated, mapped and Place-and-routed the design and the generated bit file was downloaded to the FPGA and via UART comunication I can communicate with the design.
I wanted to do a post-place-and-route simulation to see the behavior of desgn but I received the following error message in mapping process :
Can anybody let me know where could be the problem that prevents the simulation? I have to mention that the Behavioral and post-translate simulations are performed correctly !
Remark: Is it related to the branch taken from the output of IBUFG?? I just conjectured it !
Any kind assistance is cordially appreciated,
Regards,
Hello,
I encountered an strange error during the post-place and route simulation of my design that I would like to share it here for a possible solution.
I have a design that one of its parts is operating at high frequency and the rest at low frequency.
I used the IBUFG buffer to buffer the input clock signal and the output of this IBUFG buffer goes to:
1. A PLL to generate a higher frequency
and
2. directly connected to the clock input of the module that is operating at low frequency.
Then I synthesized, translated, mapped and Place-and-routed the design and the generated bit file was downloaded to the FPGA and via UART comunication I can communicate with the design.
I wanted to do a post-place-and-route simulation to see the behavior of desgn but I received the following error message in mapping process :
Code:
=======ERROR:Anno:169 - Encountered bel type that is not handled
ERROR:NetListWriters:528 - Unsuccessfull design annotation.
Can anybody let me know where could be the problem that prevents the simulation? I have to mention that the Behavioral and post-translate simulations are performed correctly !
Remark: Is it related to the branch taken from the output of IBUFG?? I just conjectured it !
Any kind assistance is cordially appreciated,
Regards,