A small query on this small verilog code ?

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hcu

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Hello,


how can i write the "second always block" to look as a "first always block". I tried with a "for loop" but the simulator returns error.
my intent is to reduce the no.of lines.

Here a sample code:
Code: 
module example(
    
	 input clk,
	 input rst,
	 input vld,
	 input [15:0] data_in,
	 output reg data_out
	 );
	 
reg [3:0] delta [3:0];	
reg [3:0] beta [3:0];	
integer i;

//first block
	always@(posedge clk)
		if(vld)
			begin
					delta[0] <= data_in[3:0];
					delta[1] <= data_in[7:4];
					delta[2] <= data_in[11:8];
					delta[3] <= data_in[15:12];
			 end
//second block
	always@(posedge clk)
		if(vld)
			begin
				for(i=0;i<=3;i=i+1) begin
					beta[i] <= data_in[(4*(i+1))-1:(4*i)] ;
				end
			end
endmodule


suggest me the way, In my real scenario .i have to do it for about 100's of lines at various locations.
 
Last edited:

One of these options will work:
Option 1: Use a geerate
Code Verilog - [expand]
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//integer i;
 
generate genvar i;
  for (i=0;i<3;i=i+1) begin
    always @(posedge clk)
      if (vld)
        beta[i] <= data_in[4*(i+1))-1:(4*i)];
  end
endgenerate


Option 2: use the proper bit slice operation to ensure the slice width is a constant...
Code Verilog - [expand]
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integer i;
 
  always @(posedge clk)
    if (vld)
      for (i=0;i<3;i=i+1) begin
        beta[i] <= data_in[4*i +:4];
      end
 

Can be done without a for loop in SystemVerilog

Code: 
[FONT=Courier New]beta <= {<<4{data_in}};[/FONT]

Even simpler if you change the array declaration ordering of beta

Code: 
[FONT=Courier New]reg [3:0] beta [0:3];	

beta <= {>>{data_in}};[/FONT]
 

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