A simple write transaction for AHB protocol

// Code your testbench here
// or browse Example
parameter data_width	=8;
parameter addr_width	=32;
parameter seq			=2'b00;
parameter non_seq		=2'b01;
parameter hsize         =4;

interface ahb_inter();
  bit hclk=0;
  bit hreset;  
  bit[1:0] htrans;
  modport ahb_write(output hclk,hreset,htrans); 
  
endinterface  

typedef enum {READ,WRITE}tr_type_t;

class ahb_trns;
  rand bit[data_width-1:0] hwdata[1];
  rand bit[addr_width-1:0] hwaddr;
  rand bit                 hwrite;
  rand tr_type_t tr_type;   
 
endclass
     

class ahb_driver; 
  ahb_trns m_trns;
  virtual ahb_inter.ahb_write ahb_inf;

  function new(virtual ahb_inter.ahb_write ahb_inf);
  this.ahb_inf=ahb_inf; 	
  m_trns=new();  
  	this.m_trns=m_trns;
endfunction
   
task run;
  //reg[31:0] mem[1];
  for(int i=0;i<hsize;i=i+1)
  begin
	   m_trns.randomize();
   if(!ahb_inf.hreset)
    begin
     foreach(m_trns.hwdata[i])
      begin
       @(posedge ahb_inf.hclk)
          begin
  			m_trns.hwrite=(m_trns.tr_type ==WRITE)? 1:0;
            m_trns.hwaddr=(m_trns.hwrite)?m_trns.hwdata[i]:1'bx;
            
          end
   	   end 
    end
    $display("hclk=%d,hreset=%d,htrans=%d,hwrite=%d,hwaddr=%d,hwdata=%p",ahb_inf.hclk,ahb_inf.hreset,ahb_inf.htrans,m_trns.hwrite,m_trns.hwaddr,m_trns.hwdata);
    
  end    
endtask

endclass 
  
module ahb_write;
  ahb_inter ahb_if();  
  always #1 ahb_if.hclk=~ahb_if.hclk;
  initial
    begin
      ahb_driver ahb_drv=new(ahb_if);
      ahb_drv.ahb_inf= ahb_if;// interface is copied to virtual interface of driver
      repeat(4) ahb_drv.run();
      ahb_if.hreset=1;
      #5 ahb_if.hreset=0;
      $monitor("hclk=%d",ahb_if.hclk);
      $dumpfile("ahb_write.vcd");
      $dumpvars(0,ahb_if.hclk,ahb_if.hreset);
      #100 $finish;
    end
endmodule