A simple Verilog question about rising edge of a signal

[nervecell_23]

Hi guys,

I want to set a signal HIGH for only one clock cycle at the rising edge of another signal, can I use the following code?

always@((posedge clk)&&(posedge SIGNAL))
begin
    .......
end

Thanks!

 

[pedroromanvr]

Can you explain it more? Do you want to set a signal using two clocks?

 

[vardan]

Assume you need an edge detecting circuit.

assign out = Q1 & (!Q2);
always @(posedge clk or negedge rst)
	if (!rst)
		begin
			Q1 <= 1'b0;
			Q2 <= 1'b0;
		end
	else
		begin
			Q1 <= In;
			Q2 <= Q1;
		end

 

[manu.srg]

I think you can. But how you are going to limit it for one clock cycle?