ash72
Newbie level 5
The spec "A request must be followed by a grant (in the next cycle)".
I was given a solution for this spec using VHDL assert, as follows:
prev_req <= req when rising_edge(clk);
assert_grant_follows_request : process(clk, reset)
begin
if rising_edge(clk) and reset = '0' then
assert prev_req = '0' or grant = '1';
end if;
end process;
My question is : What's the need for the signal prev_req? Why can't we just have "assert req = '0' or grant = '1'"? Why are we creating prev_req to be used in the assertion? Has this something to do with delta delay?
Thanks.
I was given a solution for this spec using VHDL assert, as follows:
prev_req <= req when rising_edge(clk);
assert_grant_follows_request : process(clk, reset)
begin
if rising_edge(clk) and reset = '0' then
assert prev_req = '0' or grant = '1';
end if;
end process;
My question is : What's the need for the signal prev_req? Why can't we just have "assert req = '0' or grant = '1'"? Why are we creating prev_req to be used in the assertion? Has this something to do with delta delay?
Thanks.