yyffe
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Hello everyone,
I'm using siliconsmart for library characterization, the model I'm using is BSIMCMG and PTM.
BSIMCMG describes the mathematical model of finfet in verilog-A. PTM lists process parameters in their model files.
When I was trying to import the spice netlists, I got the following error messages on every netlist:
Error: parse failed : 22
Warning: The port Y is not in the node map. It may be a floating port.
Warning: The port A is not in the node map. It may be a floating port.
......
I searched online, turned out it might caused by incorrect process model including.
Am I suppose to include all model files in configure.tcl like this? Everything seems fine when I used the following statements during HSPICE simulation (without "{" and "}" of course).
{.inc "xxx/xxx/xxx.pm"}
{.hdl "xxx/xxx/xxx.va"}
{.lib "xxx/xxx/param.inc" 7nm}
......
I actually wrote the instances files by myself and continued characterizing.
But the resulting library seems less convincing because of this problem, especially when results of some gates do not make sense.
Thanks
by Yu
I'm using siliconsmart for library characterization, the model I'm using is BSIMCMG and PTM.
BSIMCMG describes the mathematical model of finfet in verilog-A. PTM lists process parameters in their model files.
When I was trying to import the spice netlists, I got the following error messages on every netlist:
Error: parse failed : 22
Warning: The port Y is not in the node map. It may be a floating port.
Warning: The port A is not in the node map. It may be a floating port.
......
I searched online, turned out it might caused by incorrect process model including.
Am I suppose to include all model files in configure.tcl like this? Everything seems fine when I used the following statements during HSPICE simulation (without "{" and "}" of course).
{.inc "xxx/xxx/xxx.pm"}
{.hdl "xxx/xxx/xxx.va"}
{.lib "xxx/xxx/param.inc" 7nm}
......
I actually wrote the instances files by myself and continued characterizing.
But the resulting library seems less convincing because of this problem, especially when results of some gates do not make sense.
Thanks
by Yu