Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

A question of jitter vs OSR in delta sigma adc design

Status
Not open for further replies.
J

jnuhope

Member level 2
Joined
Apr 10, 2007
Messages
51
Helped
4
Reputation
8
Reaction score
0
Trophy points
1,286
Activity points
1,566
In Boser and Wooley's classic delta sigma paper it says:

The error caused by clock jitter is inversely proportional to the OSR and since the in-band quantization noise is inversely proportional to the fifth power of OSR, the amount of clock jitter that can be tolerated decreases for an increase in oversampling ratio.

My question is: since the error caused by jitter is inversely proportional to OSR, why it says the jitter that can be tolerated decreases for an increase in OSR? Anyone can help me understand this?

Thanks in advance!
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top