jihrenee
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I'm designing the bias circuit for the Maneatis Cell.
I have a question about this bias circuit,
When Vctrl increased to a high value, say VDD,
the output of the OPAMP will almost zero,
turning off the NMOS which provides the current to the cell.
So, the VCO won't oscillate.
My question is, due to this phenomenon, i shouldn't let Vctrl to rise up to VDD?
I have a question about this bias circuit,
When Vctrl increased to a high value, say VDD,
the output of the OPAMP will almost zero,
turning off the NMOS which provides the current to the cell.
So, the VCO won't oscillate.
My question is, due to this phenomenon, i shouldn't let Vctrl to rise up to VDD?
