Feb 18, 2006 #1 H hardnova Newbie level 1 Joined Feb 18, 2006 Messages 1 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,281 Activity points 1,285 Has anyone here ever used Active-HDL 7.1 (Design & Verification tool) to program before? If so, what did you make and how was it used.
Has anyone here ever used Active-HDL 7.1 (Design & Verification tool) to program before? If so, what did you make and how was it used.
Feb 19, 2006 #2 S saudrehman Member level 1 Joined Dec 20, 2005 Messages 40 Helped 1 Reputation 2 Reaction score 0 Trophy points 1,286 Activity points 1,697 The Active-HDL suite is a IDE for digital IC (FPGA) design and verification that employs hardware description languages and C/C++ solutions. It gives tools for efficient and vendor independent design implementation and testing.
The Active-HDL suite is a IDE for digital IC (FPGA) design and verification that employs hardware description languages and C/C++ solutions. It gives tools for efficient and vendor independent design implementation and testing.