a question about lvs, help!!

[tinybull]

I want to do lvs on a whole chip.And find the cdl of sram can not be imported.
The error information is :
*/WARNING : UNDEFINE PIN :Q IN MODULE :RA1SD
IGNORED WHEN THE EXPLICIT FLOATING PORT FUNCTION IS ON
*/WARNING : UNDEFINE PIN :Q IN MODULE :RA1SD
IGNORED WHEN THE EXPLICIT FLOATING PORT FUNCTION IS ON
........
IGNORED WHEN THE EXPLICIT FLOATING PORT FUNCTION IS ON

IGNORED WHEN THE EXPLICIT FLOATING PORT FUNCTION IS ON

*/ERROR : UNMATCHED PIN AND NET NUMBER IN LINE: 22353

*/ERROR : UNDEFINE MODULE :,

I think this due to the the multibit bus expression difference in sram cdl
and whole chip netlist .
in sram cdl
.SUBCKT RA1SD A[0] A[1] A[2] A[3] A[4] A[5] A[6] A[7] A[8] A[9] A[10] A[11]
+ CEN CLK D[0] D[1] D[2] D[3] D[4] D[5] D[6] D[7] Q[0] Q[1] Q[2] Q[3] Q[4]
+ Q[5] Q[6] Q[7] WEN

but in whole-chip netlist:
RA1SD ra1sd0 ( .Q ({ ram_p_data_rd[31] , ram_p_data_rd[30] ,
ram_p_data_rd[29] , ram_p_data_rd[28] , ram_p_data_rd[27] ,
ram_p_data_rd[26] ,
ram_p_data_rd[25] , ram_p_data_rd[24] })
The netlist is P&R by siliconensemble .And the sram cdl is generated by tsmc memory compiler.
I don't know how to do .Can someone tell me ?